In order to make a communication system operate normally, the system's clock and data must meet certain jitter requirements. Therefore, some communication equipments must be equipped with a jitter-attenuating function to wipe off the signal jitter generated during the communication, so as to guarantee accuracy and reliability of the signal reception. Accordingly, a series of international standards and protocols have been presented to regulate de-jittering standards. At present, jitter attenuation of E1 (2048 Kbits/s PCM communication system) and T1 (1544 bits/s PCM communication system) line interface transceivers should follow related protocols such as:
Jitter attenuation protocols for E1 signals include: ITU-T I.431, G.736 . . . 739, G.823 and ETSI TBR12/13;
Jitter attenuation protocols for T1 signals include: PUB62411, PUB43802, TR-SSY 009, TR-TSY 253, TR-TSY 499 and ITU-T I.431, G.703 and G.824.
In order to guarantee the system's de-jittering performance, corresponding templates concerning the system's de-jittering performance requirements have already been set up at present so as to check whether the de-jittering performance of the system based on the template meets relevant requirements. For instance, when measuring the Jitter Transfer Function (JTF), the testing instrument adds jitters to certain frequency points in the transmitted data, and then measures the jitters at corresponding frequency points in the received data; by taking the ratio of a received jitter and an added jitter (generally jitter attenuation with dB unitage) as a vertical coordinate, and taking the frequencies at which the jitters are measured as a horizontal coordinate, a jitter transfer function curve can be formed by connecting these coordinate points. FIGS. 1 and 2 are jitter transfer curve templates of E1 signals regulated in G.736 and that of T1 signals regulated in PUB62411 respectively. The curves of both templates are similar to a frequency response curve of a first-order low-pass filter. The curve obtained by measurement of G.736 template should be below the template curve; while the curve obtained by measurement of PUB62411 template should be between the two template curves. In order to reach this objective, the apparatus must be equipped with jitter-attenuating function. When receiving or transmitting a signal, the data signal's can be de-jittered through the following steps of: extracting a clock from the data with jitter, generating the clock with low jitter by processing the extracted clock via a de-jittering circuit, and then transmitting the signal by this low-jitter clock.
At present, conventional de-jittering method is to use an analogue phase-locked loop de-jittering circuit. The analogue phase-locked loop de-jittering circuit is shown in FIG. 3, which includes: First Input First Output (FIFO) 301, frequency divider by 16 (DIV16) 302, frequency divider by 64 (DIV64) 303, Phase detector (PD) 304, Digital Control Synthesizer (DCS) 305 and Analogue Phase-locked Loop (APLL) 306.
Taking E1 signal transmission system for example, the high-quality 2 MHz (which is practically 2.048 MHz and abbreviated as 2M for convenience) clock outputted by a crystal oscillator is inputted to APLL 306 as the reference clock of APLL 306. APLL 306 outputs a 32 MHz clock that is generated by Voltage Controlled Oscillator (VCO) inside APLL and is of very low jitter. Then, this 32 MHz clock is inputted to the frequency divider by 16 (DIV16) 302 and the desired 2 MHz clock without jitter can be obtained after the frequency division by 16, and the obtained 2 MHz clock is inputted to First Input First Output (FIFO) 301.
It can be seen from the jitter transfer curve templates in FIGS. 1 and 2 that, the corner frequency of jitter attenuation is as low as a few Hz, which requires a number of counting times. Therefore, the 2 MHz clock without jitter, which is outputted to First Input First Output (FIFO) 301, is also inputted to the frequency divider by 64 (DIV64) 303 for frequency division by 64, and the divided signal is then outputted to Phase detector (PD) 304 for phase discrimination, so that there are a number of counting times. Phase detector (PD) 304 outputs a digital control signal to control the counting and accumulating of Digital Control Synthesizer (DCS) 305, synthesizes the 32M clock outputted by Analogue Phase-locked Loop (APLL) 306 into a signal having the same frequency as that of the crystal oscillator clock, and then feeds this signal back to Analogue Phase-locked Loop (APLL) 306. It can also be seen from FIG. 3 that the data signal can be de-jittered by writing the data into FIFO based on the clock CK_EXT extracted from data and reading the data from FIFO based on the post-de-jitter clock.
In this method, because the outputted de-jittered clock is generated by an analogue circuit, the clock should be of high quality theoretically. However, a large feedback loop circuit, which contains an analogue phase-locked loop, digital circuits (including DCS and PD) and so on, is of a complicated structure. And the complicated structure, especially the complexity of the feedback loop circuit with both digital and analogue circuit, will make it difficult to calculate the quantified parameters of the circuit's de-jittering performance, thus difficult to obtain accurate design. What's more, compared with a single analogue circuit or digital circuit, a circuit structure mixed by digital and analogue circuits makes analog simulation difficult, which increases the difficulty of circuit design. The complicated structure brings another obvious disadvantage of which circuit chip dimension is large with low efficiency. In addition, the above-mentioned de-jittering circuit cannot change frequency of the outputted de-jittered clock while de-jittering, so that it is impossible to read the T1 data with the clock frequency of E1 after the T1 data is written into FIFO. In other words, it is very difficult to transfer between T1 clock and E1 clock by using the above-mentioned de-jittering method.
Besides, a de-jittering method for a clock signal is also put forward in U.S. Pat. No. 5,162,746 in the United States, which is titled Digitally Controlled Crystal-Based Jitter Attenuator. The key idea of this scheme is to adopt a digital phase-locked loop and digitally controlled crystal to generate the output clock. Circuit schematic of this method is shown in FIG. 4. This circuit includes: a first divider 401, a second divider 402, divider by 4 403, digital phase detector 404 and digitally controlled crystal oscillator 405.
Therein, digital phase detector 404 receives the clock with jitter that is divided by the first divider 401 and the feedback clock that is divided by the second divider 402, and compares both of them, then outputs a multi-bit digital control signal to digitally controlled crystal oscillator 405. Then, digitally controlled crystal oscillator 405 outputs a clock signal according to this control signal, and a de-jittered clock is outputted after being processed by divider by 4 403. The de-jittered clock is also outputted to the second divider 402 as a feedback clock.
The above-mentioned multi-bit digital control signal can reflect phase difference between the two clocks, and the digitally controlled crystal oscillator 405 can be accurately controlled according to this multi-bit digital control signal. Inside the digitally controlled crystal oscillator 405 there are multilevel operational amplifiers with a capacity load, and changing the load capacity through the digital control signal can change the crystal frequency.
In addition, by changing division value of the first divider 401 and that of the second divider 402 in FIG. 4, bandwidth of the whole digital phase-locked loop can be adjusted so as to meet different applications.